1. Field of the Invention
The principles of the present invention generally relate to liquid crystal display (LCD) devices and their methods of fabrication. More particularly, the principles of the present invention relate to an LCD device having a storage capacitor and a simplified method of fabricating the same.
2. Discussion of the Related Art
As demand for information displays and applications for portable information devices increase, thin film type flat panel display (FPD) devices have been actively researched and developed. Of the various types of FPD devices, LCD devices are particularly beneficial as the LCD panels provided therein express images at high resolution and excellent color quality. Accordingly, LCD devices are often incorporated within notebook computers, desktop monitors, and the like.
LCD panels typically include a color filter substrate, an array substrate bonded to the color filter substrate, and a liquid crystal layer formed between the color filter and array substrates. The array substrate typically includes a plurality of switching devices (i.e., thin film transistors (TFT)) arranged in a matrix pattern. Each TFT generally includes a thin film of amorphous or polycrystalline silicon as an active pattern through which a channel is selectively defined.
FIG. 1 illustrates a partial plan view of a related art array substrate. It will be appreciated that the related art array substrate includes a plurality of pixels, each defined by a crossing of a plurality of gate lines and data lines. Thus, and for simplicity in illustration, only one pixel of the related art array substrate will be discussed with respect to FIG. 1.
Referring to FIG. 1, the array substrate 10 supports horizontally oriented gate lines 16 and vertically oriented data lines 17 defining a pixel region. A TFT is formed at the crossing of a gate line 16 and a corresponding data line 17 and a pixel electrode 18 is formed within each pixel region.
Each TFT includes a gate electrode 21 connected to the gate line 16, a source electrode 22 connected to the data line 17, a drain electrode 23 connected to the pixel electrode 18, and an active pattern 24 formed of polycrystalline silicon, through which a conductive channel region is defined between the source and drain electrodes 22 and 23 when a gate voltage is supplied to the gate electrode 21.
A pair of first contact holes 40A are formed through first and second insulation films (not shown) to enable electrical connection between the source electrode 22 and a source region of the active pattern 24 as well as between the drain electrode 23 and a drain region of the active pattern 24. A second contact hole 40B is formed through a third insulation film (not shown) to enable electrical connection between the drain electrode 23 and the pixel electrode 18.
Having described the array substrate above, a method of fabricating the related art array substrate according to a related art process will now be described in greater detail with reference to FIGS. 2A to 2F.
Referring to FIG. 2A, an active pattern 24 is formed by depositing a polycrystalline silicon thin film on a substrate 10 and, in a first photolithographic masking process, patterning the as-deposited thin film.
Referring to FIG. 2B, a first insulation film 15A and a conductive metal layer are sequentially deposited over the entire surface of the substrate 10 and on the active pattern 24. After being deposited, the conductive metal material is patterned in a second photolithographic masking process to form the gate electrode 21 over the active pattern 24 and separated therefrom by the first insulation film 15A.
Subsequently, p+ type or n+ type source/drain regions 24A/24B are formed at predetermined regions of the active pattern 24 by implanting impurity ions at a high density using the gate electrode 21 as a mask. Thus, the source/drain regions 24A/24B, separated by a channel region 24C, ohmically contact subsequently formed source/drain electrodes.
Referring to FIG. 2C, a second insulation film 15B is deposited over the entire surface of the substrate 10 and on the gate electrode 21. The first and second insulation films 15A and 15B are then patterned in a third photolithographic masking process removed to form a pair of first contact holes 40A that exposes portions of the source/drain regions 24A/24B.
Referring to FIG. 2D, a conductive metal material is then deposited over the entire surface of the substrate 10, within the pair of first contact holes 40A, and patterned in a fourth photolithographic masking process to simultaneously form the source and drain electrodes 22 and 23, each contacting the respective ones of the source and drain regions 24A and 24B via the pair of first contact holes 40A. As shown, a portion of the conductive metal layer is patterned so as to extend from the source electrode 22, thereby forming the data line 17.
Referring to FIG. 2E, a third insulation film 15C is deposited over the entire surface of the substrate 10 and is patterned in a fifth photolithographic process to form a second contact hole 40B, exposing a portion of the drain electrode 23.
Finally, and with reference to FIG. 2F, a transparent conductive metal material is deposited over the entire surface of the substrate 10, within the second contact hole 40B, and patterned in a sixth photolithographic masking process to form a pixel electrode 18 connected with the drain electrode 23.
As discussed above, the related art method of fabricating array substrate that incorporate polycrystalline silicon TFTs illustrated in FIG. 1 requires six photolithographic masking processes to form the active pattern 24, the gate electrode 21, the pair of first contact holes 40A, the source/drain electrodes 24A/24B, the second contact hole 40B, and the pixel electrode 18. It is generally known that a photolithographic mask process requires many sub-processes such as cleaning, photoresist deposition, exposure with expensive masks, developing, etching, stripping, inspection, etc. Thus, any method of fabricating array substrates that uses a large amount of photolithographic processes may result in a reduced production yield and increase the cost of fabrication.